EVALUATING PERFORMANCE OF CHIP MULTI-CORE WITH CACHE LEVEL

Ho Khanh Lam; Du Dinh Vien; Vu Ngoc Hung; Nguyen Duy Viet; Pham Van Hai

Ho Khanh Lam Hung Yen University of Technology and Education
Du Dinh Vien Hung Yen University of Technology and Education
Vu Ngoc Hung Hung Yen University of Technology and Education
Nguyen Duy Viet Hung Yen University of Technology and Education
Pham Van Hai Hung Yen University of Technology and Education

Keywords: Chip multi-core, Multiple Job Class Product Form Closed Queueing Network (MCPFCQN), performance

Abstract

Chip multi-core are applied widely in hight performance computer systems and supercomputers. The performance of CMPs with applications of cache multi-level structures is interested in many researchers. There are many solutions used to evaluate the performance of MCP. For this objective, the paper proposes an approach that uses MCPFCQN. The performance of CMP is characterised by 05 parameters: number of jobs, waiting time, response time, utilization and capacity. The results show that when the number of caches increases, number of jobs, waiting time, utilization and capacity are increased too, but only response time is deacreased

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