EVALUATING PERFORMANCE OF CHIP MULTI-CORE WITH CACHE LEVEL

Ho Khanh Lam; Du Dinh Vien; Vu Ngoc Hung; Nguyen Duy Viet; Pham Van Hai

Ho Khanh Lam Hung Yen University of Technology and Education
Du Dinh Vien Hung Yen University of Technology and Education
Vu Ngoc Hung Hung Yen University of Technology and Education
Nguyen Duy Viet Hung Yen University of Technology and Education
Pham Van Hai Hung Yen University of Technology and Education

Abstract

Chip multi-core are applied widely in hight performance computer systems and supercomputers. The performance of CMPs with applications of cache multi-level structures is interested in many researchers. There are many solutions used to evaluate the performance of MCP. For this objective, the paper proposes an approach that uses MCPFCQN. The performance of CMP is characterised by 05 parameters: number of jobs, waiting time, response time, utilization and capacity. The results show that when the number of caches increases, number of jobs, waiting time, utilization and capacity are increased too, but only response time is deacreased

References

J. Virtamo, “Queueing Theory / Probability Theory”, www.netlab.hut.fi/opetus/.

Kiran M Rege, “Multi-class Queueing Models for Performance Analysis of Computer Systems”, December 1990, Volume 15, Issue 4, pp. 355–363. DOI: 10.1007/BF02811331.

Jackson, R. R. P. (1995). “Book Review: Queueing Networks and Product Forms: A Systems Approach”. IMA Journal of Management Mathematics. 6 (4): 382–384. doi:10.1093/imaman/6.4.382.

Daniel Sanchez, George Michelogiannakis, and Chitistos Kozyrakis, “An Analysis of On-Chip Interconnection Networks for Large-Scale Chip Multiprocessors”. Stanford University. ACM Transactions on Architecture and Code Optimization, Vol. 7, No. 1, Article 4, Publication date: April 2010.

David Wentzlaff et all, “On – chip Intercinnection Architecture of the Title Processor”. 0272- 1732/07/$20.00 G 2007 IEEE. Published by the IEEE Computer Society. Authorized licensed use limited to: The University of Toronto. Downloaded on January 4, 2010 at 12:39 from IEEE Xplore.

D. N. Jayasimha, Bilal Zafar, Yatin Hoskote,“On-Chip Interconnection Networks: Why They are Different and How to Compare Them”.

Jesús Camacho Villanueva et all, “A Performance Evaluation of 2D-Mesh, Ring, and Crossbar Interconnects for Chip Multi-Processors”. NoCArc ‘09, December 12, 2009, New York City, New York, USA Copyright © 2009 ACM 978-1-60558-774-5.

B. Krishna Priya, Amit D. Joshi, N. Ramasubramanian, “A Survey on Performance of On-Chip Cache for Multi-core Architecture”, Pondicherry, India — August 25 - 26,2016ISBN:978-1-4503- 4756-3.

Jie Tao, Marcel Kunze, Fabian Nowak, Rainer Buchty, Wolfgang Karl, “Performance Advantage of Reconfigurable Cache Design on Multicore Processor Systems”, Int J Parallel Prog (2008) 36:347–360. DOI 10.1007/s10766-008-0075-4.

Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser, “Nahalal: Cache Organization for Chip Multiprocessors”, Manuscript submitted: 24-Apr-2007. Manuscript accepted: 23-May-2007. Final manuscript received: 29-May-2007.

Muhammad Ali Ismail, “Performance Behavior Analysis of the Present 3-Level Cache System for Multi-Core Systems using Queuing Modeling”, International Conference on Latest Computational Technologies (ICLCT’2012) March 17-18, 2012 Bangkok.